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Feb 20, 2025

ISSCC: on-chip temperture sensors

Two papers at the International Solid-state Circuits Conference tackled ultra-low power on-chip temperature sensing, one using an npn transistor and the other by sensing a wire. The npn sensor

Two papers at the International Solid-state Circuits Conference tackled ultra-low power on-chip temperature sensing, one using an npn transistor and the other by sensing a wire.

The npn sensor digitises using a noise-optimised charge-balancing continuous-time ΔΣ-modulators to measure PTAT (proportional to absolute temperature) current (from ΔVbe between two transistors operating at different currents) and CTAT (complementary to absolute temperature) voltage (Vbe) from which temperature can be determined after a one-point trim.

In the circuit shown, Vbe is converter to a CTAT current by a virtual ground resistor, and the two currents are balanced by the feedback from ΔΣ-modulation.

The particular scheme chosen favours the signal-to-noise ratio of the smaller PTAT signal, with is about an order of magnitude smaller than the more robust CTAT signal, improving overall resolution.

Fabricated on a 0.18μm cmos process, the sensor occupies 0.05mm2 (decimation filter off-chip) and draws 1.8μA from 1.4V.

The sensor has an untrimmed inaccuracy of 0.9°C, improving to 0.5°C after a single-point PTAT trim. Further compensation for resistor variation achieves a final inaccuracy of 0.1°C.

An energy figure-of-merit of 80fJK2 was achieved.

A metal wire sensor was picked for the second temperature measuring design because it is aimed 28nm cmos ICs.

Metal sheet resistance and metal layer count increase as processes shrink.

By using five metal layers (with shields above and below), a 25kΩ sensing resistor was implemented in 12% less space than a similar 28nm silicide-diffusion resistor – which would be the type of sensing resistor traditionally used in, for example, a 0.18μm process where low sheet resistance and layer count tip the size balance the other way.

A frequency-locked loop was picked to read the resistor, consisting of a time-domain amplifier (TDA), a phase-frequency detector (PFD), a charge pump (CP), a notch filter, a voltage-controlled ring-oscillator (VCRO), a phase generator to distribute the control signals to different blocks, and a fractional-pulse extractor (FPE).

A time-domain amplifier (differential voltage to period converter) was picked in preference to the challenge of designing a deep-submicron (Vdd <1V) voltage-mode amplifier.

Using ten pulses (‘fractional pulses’) from the 5-phase output of the VCRO increased precision without increasing Fout (taking more power) or a needing a higher resistance (more area).

A small penalty was extra circuitry to mitigate the non-constant widths of the fractional pulses.

Output frequency ranged across 4.1MHz at -40°C to 2.8MHz at 125°C.

Inaccuracy was ±1.5°C after one-point trimming and ±0.2°C after two-point trimming across −40 to 125°C.

25°C consumption was 10.5μW from 0.8V, it occupies 4,100μm2, and scores 45fJK2.

ISSCC 2025

Paper 27.4 Delft University of TechnologyA BJT-based temperature sensor with an 80fJ.K2 resolution FoM

Paper 27.5 University of Macau, University of LisboaA 4,100μm2 wire-metal-based temperature sensor with a fractional-discharge FLL and a time-domain amplifier with ±0.2°C inaccuracy (3σ) from -40 to 125°C and 45fJ·K2 resolution FoM in 28nm cmos

Note: some readers will notice that this ISSCC energy harvesting article also featured designs from Delft University of Technology, the University of Macau and the University of Lisboa.There was no skulduggery – the papers were picked only for their design interests, and without reference to the source organisations – but hats off to them for fine low-power design.